The present invention relates to semiconductor integrated circuits, and, more particularly, to low power integrated circuits.
Many applications call for low power integrated circuits, such as battery powered or parasitically powered integrated circuits used for cordless identification tags, medical diagnostics devices, and data and communication modules. For example, the DS1992 Touch Memory.TM. manufactured by Dallas Semiconductor Corporation in Dallas, Tex. includes a read/write memory with battery in a coin-sized can with the front and back of the can forming two electrodes for 1-wire communication with the memory. The memory retains data for 10 years, and thus the memory must have very low power consumption. Similarly, the DS1287 real time clock module for AT-class personal computers includes a battery and crystal plus an integrated circuit for timekeeping even when a personal computer is powered down.
The preferred embodiment illustrated in FIGS. 1A-C limits power consumption by, among other methods, subdividing the integrated circuit into different portion which are separately powered by different power sources. In particular, the one-wire communication portion derives its power by parasitic tapping power from the communication bus; thus upon disconnection, the communication portion has a power failure. Contrarily, the memory and clock portions remains continually powered up by a battery. The use of two power sources requires a voltage level translator between the portions because the battery and the parasitic power sources may be at different voltages. And such a level translator must also have low power consumption, especially when the communication portion has its power source removed: floating nodes could lead to significant leakage currents and drain the battery. Also, the input buffers in the communication portion must not permit large transition currents when the voltage slowly rises and falls on the communication bus due to the possibly large capacitive loading of the communication bus in certain applications.
Indeed, the preferred embodiment has level translators which provide communication between domains of different power supplies by one-shot pulses, and the input buffer includes CMOS inverters with resistive current limitations to reduce power consumption during slowly varying inputs while retaining fast switching.